Complementary metal-oxide-semiconductor (CMOS) integrated circuits employ both n-channel metal-oxide-semiconductor field-effect transistor (MOSFETs), in which current is carried by electrons, and p-channel MOSFETs, in which current is carried by holes. It is well known that electron and holes mobility have different dependencies on the crystallographic orientation of a semiconductor substrate. For silicon, the optimal electron mobility parallel to the substrate surface is achieved with a (100) orientation, whereas the optimal hole mobility is achieved with a (110) orientation. Conventional bulk and silicon-on-insulator (SOI) wafers provide a single crystal orientation, forcing a device designer to choose between optimal electron and hole mobility.
In recent years, several techniques have been proposed as a means to simultaneously achieve optimal electron and hole mobilities in CMOS integrated circuits. In these processes, n-channel and p-channel MOSFETs are fabricated in different areas of the wafer, having (100) and (110) orientations, respectively. An approach based on vapor-phase epitaxy is described in the article by Yang et al., IEDM 2003, pages 453-456. In this approach, a thin silicon layer of one orientation, for example (110), is bonded to an oxidized wafer of a different orientation, for example (100), thus obtaining a SOI wafer with a (110) top silicon layer and a (100) substrate. The top silicon layer and buried oxide are then selectively etched away and (100)-oriented silicon is epitaxially grown, for example by rapid thermal chemical vapor deposition, in areas where n-channel MOSFETs are to be formed. Another approach, based on solid-phase epitaxy, is described in the article by Sung et al., IEDM 2005, pages 225-228. In this approach, a thin silicon layer of one orientation, for example (110), is bonded to a wafer of a different orientation, for example (100), without an intermediate buried oxide. The top (110) silicon layer is then selectively amorphized by ion implantation and (100) regions are formed by solid-phase epitaxy by a process called amorphization-templated recrystallization (ATR). This oxide-free fabrication process is called direct silicon bonding (DSB). Further details and variations on the DSB process may be found for example in U.S. Patent Application Publication No. 2006/0276011 to Fogel et al.
One potential issue with the DSB process is that silicon layers of different orientations come into direct contact, and the resulting interface may include defects due to lattice mismatch. This may cause leakage currents parallel to the surface of the wafer. Another source of leakage may be the possible buildup of dopants at the interface between layers of different orientations, with associated increase of band-to-band tunneling due to the enhanced electric fields in the higher-doping region. Leakage currents are undesirable because they increase power consumption when a transistor is in the off-state.